1. Technical Field
The inventive concept relates to a vertical semiconductor device, and more particularly, to a semiconductor device including a cell having a vertical channel structure capable of minimizing a floating body effect.
2. Related Art
With a high integration degree of semiconductor devices, dynamic random access memories (DRAMs) of below 40 nm grade have been is demanded to improve the degree of integration. However, it is very difficult to scale down below 40 nm in a planar or recess gate transistor used in 8F2 (F: minimum feature size) or 6F2 cell architecture. Accordingly, DRAMs having 4F2 cell architecture have been demanded to improve the degree of integration by one-and-a-half to two times at the same scaling.
To constitute 4F2 cell architecture, a source unit and a drain unit of a cell transistor, that is, the source unit of a capacitor formation region in which charges are stored and the drain unit from which charges are drained to a bit line, need to form in 1F2. Recently, a vertical cell transistor structure in which a source unit and a drain unit are formed in 1F2 has been studied. In the vertical cell transistor structure, a source region and a drain region of a transistor for driving a cell are formed to be vertically disposed and the transistor is driven through a channel having a vertical pillar shape. That is, the structure that a source region and a drain region are horizontally formed in 8F2 is replaced with the structure that a source region and a drain region are vertically formed so that an operation of a cell transistor can be implanted in 4F2.
In 1F2 cell architecture, a bit line junction region is formed in a side of a lower portion of a pillar in a one side contact (OSC) type.
Thereby, when the bit line junction region is formed with a shallow depth, a gate does not overlap with the bit line junction region and channel length and resistance are increased, so that a threshold voltage is increased and a channel current is reduced.
On the other hand, when the bit line junction region is formed with a greater depth to overlap the gate, a width of the pillar is narrower so that a floating body effect where a channel region is isolated from a substrate by the bit line junction region is caused.